Two terminal resistive switching device structure and method of fabricating

ABSTRACT

A semiconductor device having a memory device includes a semiconductor substrate, a first dielectric layer disposed above the semiconductor substrate, a first adhesion layer disposed upon the first dielectric layer, a bottom wiring metal disposed upon the first adhesion layer, a first barrier layer disposed upon the bottom wiring metal, a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions, a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles, a second barrier layer disposed upon the conductive metal material, a top wiring metal disposed upon the second barrier layer, and wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to and is continuation of U.S. patent application Ser. No. 12/835,704, filed on Jul. 13, 2010 and is incorporated in its entirety for all purposes.

BACKGROUND

The present invention is in general related to two terminal devices. More particularly, embodiments of the present provide a method and a structure for a two terminal switching device. The two terminal switching device can be used as a non-volatile resistive switching memory with random access and fast switching characteristics.

The success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) approach sizes less than 100 nm, problems such as short channel effect start to prevent proper device operation. Moreover, such sub 100 nm device size can lead to sub-threshold slope non-scaling and also increases power dissipation. It is generally believed that transistor based memories such as those commonly known as Flash may approach an end to scaling within a decade. Flash memory is one type of non-volatile memory device.

Other non-volatile random access memory (RAM) devices such as ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM), among others, have been explored as next generation memory devices. These devices often require new materials and device structures to couple with silicon based devices to form a memory cell, which lack one or more key attributes. For example, Fe-RAM and MRAM devices have fast switching characteristics and good programming endurance, but their fabrication is not CMOS compatible and size is usually large. Switching for a PCRAM device uses Joules heating, which inherently has high power consumption. Organic RAM or ORAM is incompatible with large volume silicon based fabrication and device reliability is usually poor.

From the above, an improved semiconductor memory device and techniques are therefore desirable.

BRIEF SUMMARY OF THE PRESENT INVENTION

The present invention is in general related to two terminal devices. More particularly, embodiments of the present provide a method and a structure for a two terminal switching device. The two terminal switching device has been applied to non-volatile resistive switching memory devices. But it should be recognized that the present invention can have a broader range of applicability.

In a specific embodiment, a method for forming a two terminal switching device is provided. The method includes providing a substrate and forming a first dielectric material overlying a surface region of the substrate. A bottom wiring material is deposited overlying the dielectric material. The method includes depositing a contact material overlying the bottom wiring material and depositing a switching material overlying the bottom wiring material; including the contact material. In certain embodiment, the contact material is optional. The method forms a masking layer overlying the switching material. In a specific embodiment, the method subjects the bottom wiring material, the contact material,-and the switching material to a first etching process using the masking layer to form a first structure. The first structure includes a bottom wiring structure and a switching element. The first structure has a top surface region and a side region. In a specific embodiment, the top surface region including a top region of the switching element. The method includes depositing a second dielectric material overlying at least the first structure including the exposed top region of the switching element and an exposed portion of the first dielectric material. The method includes planarizing the second dielectric material surface overlying at least the first structure while maintaining a portion of the second dielectric material overlying the first structure. An opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region of the first structure. The method then deposits a conductive material overlying the opening region. The conductive material is in direct contact with the switching element in a specific embodiment. A top wiring material is formed overlying at least the conductive material, and a second etching process is employed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process.

In an alternative embodiment, a method for forming a two terminal switching device is provided. The method includes providing a substrate and forming a first dielectric material overlying a surface region of the substrate. A bottom wiring material is deposited overlying the dielectric material. The method includes depositing a contact material overlying the bottom wiring material and depositing a switching material overlying the bottom wiring material; including the contact material. In certain embodiment, the contact material is optional. The method forms a masking layer overlying the switching material. In a specific embodiment, the method subjects the bottom wiring material, the contact material,-and the switching material to a first etching process using the masking layer to form a first structure. The first structure includes a bottom wiring structure and a switching element. The first structure has a top surface region and a side region. In a specific embodiment, the top surface region including a top region of the switching element. The method includes depositing a second dielectric material overlying at least the first structure including the exposed top region of the switching element and an exposed portion of the first dielectric material. The method includes planarizing the second dielectric material surface overlying at least the first structure while maintaining a portion of the second dielectric material overlying the first structure. An opening region is formed in a portion of the second dielectric layer to expose a portion of the top surface region of the first structure. The method deposits a conductive material overlying the second dielectric material including the opening region in direct contact with the switching element in a specific embodiment. The method includes depositing a first adhesion layer overlying the conductive material and subjecting the first adhesion layer and the conductive material to a second pattern and etches process. The second pattern and etch process removes a portion of the conductive material and a portion of the first adhesion layer to expose a surface region of the second dielectric material while maintaining at least the conductive material and the adhesion layer at least in the opening region. A top wiring material is formed overlying the first adhesion layer and the exposed portion of the second dielectric layer. In a specific embodiment, the top wiring material is subjected to a second patterning and etching process to form a top wiring structure. In a specific embodiment, the side region of the first structure including the first side region of the switching element is free from a contaminant conductive material from the at least the second pattern and etch process and no short occurs between the top wiring structure and the bottom wiring structure.

Many benefits can be achieved by ways of the present invention. As merely an example, the present method provides a method and a structure for fabricating a switching device using a metal as a top electrode. By not exposing the sidewall of the switching material during etch of the upper electrode, this method provides device structures that are free of defects such as a short between a top electrode and a bottom electrode thereby improving device performance and device yield.

SUMMARY OF THE DRAWINGS

FIG. 1 is a simplified diagram illustrating a two terminal switching device arranged in a crossbar configuration.

FIG. 2 is a simplified diagram illustrating shorts between electrodes of a switching device.

FIGS. 3-16 are simplified diagrams illustrating a method of forming a two terminal switching device according to an embodiment of the present invention.

FIGS. 17-19 are simplified diagrams illustrating an alternative method of forming a two terminal switching device according to an embodiment of the present invention.

FIGS. 20-21 are simplified diagrams illustrating yet an alternative method of forming a two terminal switching device according to an embodiment of the present invention.

FIGS. 22-23 are simplified diagrams illustrating an method of forming a two terminal switching device according to an embodiment of the present invention

DETAIL DESCRIPTION OF THE PRESENT INVENTION

The present invention is in general related to two terminal devices. More particularly, embodiments of the present provide a method and a structure for a two terminal switching device. The two terminal switching device may be used in non-volatile resistive switching memory devices that provide for random access, fast switching, and are scalable to very small sizes. But it should be recognized that the present invention can have a much broader range of applicability.

For switching devices using resistive switching, selected materials are used for each of the electrodes or the wiring structures. For example, a noble metal such as platinum is used for a nickel oxide-based resistive switching device to provide an ohmic contact to the device and to prevent chemical reaction with the switching material. Certain solid electrolyte based (for example, GeSe) switching devices or amorphous silicon based switching devices use silver as at least one of the electrode materials or contact material for an enhanced switching performance. Theses metal materials are not commonly used in current CMOS fabrication. In particular, due to their inert nature, chemical etching of these materials is particularly challenging or impossible, making nano-scale device fabrication difficult.

FIG. 1 is a simplified diagram of a resistive switching device in a crossbar configuration though other spatial arrangements are also possible. Resistive switching device 100 includes a top wiring structure 102, a bottom wiring structure 104, and a switching layer 106 configured in an intersection region sandwiched between the top wiring structure and the bottom wiring structure. For example, the top wiring structure includes at least silver, gold, platinum, palladium, nickel, aluminum, chromium, iron, manganese, tungsten, vanadium, cobalt or other metal materials, the switching layer can comprise of a chalcogenide material such as a metal oxide material or an amorphous silicon material depending on the embodiment.

FIG. 2 illustrates a partially formed device 202. The partially formed device includes a bottom wiring structure 208, a switching element 210 and a top metal wiring structure 204. The partially formed device is formed by a simultaneous etch of top wiring material 204 and switching layer 210. As the top wiring structure is made of an inert metal for certain switching device, physical etch such as sputter etch. This etching step can result in formation of contaminant conductive materials 206 deposited on sidewall of the switching layer, as shown. The contaminant conductive material can be from the etched material from the top wiring structure or the bottom wiring structure or both and causes an electrical short between top wiring structure 204 and bottom wiring structure 208, degrading device performance and yield.

Accordingly, the present invention provides a method and a structure for forming a switching device, in particular, a resistive switching device using at least a noble metal as one of the wiring structures or both of the wiring structures. But it would be recognized that embodiments according to the present invention can be applied to other devices.

FIGS. 3-16 illustrate a method of fabricating a switching device according to an embodiment of the present invention. The method includes providing a substrate 302 including a surface region 304. The substrate can be a semiconductor substrate such as a silicon wafer and the like. In certain embodiments, the substrate can include one or more devices formed thereon. The one or more devices can include CMOS devices, and others, depending on the embodiment. As shown in FIG. 4, the method includes forming a first dielectric material 402 overlying the surface region of the substrate. The first dielectric material can be a silicon oxide or a silicon nitride or a suitable dielectric film stack including combinations of different dielectric films. The first dielectric material can be formed using techniques such as chemical deposition; including plasma enhanced chemical vapor deposition, spin on coating, a combination of these techniques, and others.

Referring to FIG. 5, the method deposits a first adhesion layer 502 overlying the first dielectric material. The first adhesion layer can be tungsten nitride, titanium, titanium nitride, tantalum or tantalum nitride or any combinations of these films or others. The first adhesion layer may be formed using a chemical deposition such as chemical vapor deposition or atomic layer deposition and the like. In other applications, physical vapor deposition such as sputtering may be used depending on the application. As shown in FIG. 6, a bottom wiring material 602 is formed overlying the first adhesion layer. The bottom wiring structure material can be copper, tungsten, aluminum or other suitable metal materials depending on the embodiment. The bottom wiring material can be deposited using techniques such as physical vapor deposition process, for example, sputtering, or evaporation. The bottom wiring material can also be deposited using chemical vapor deposition, or electrochemical methods such as electroplating or electrodeless deposition from a liquid medium, or other suitable deposition techniques including a combination. The first adhesion layer provides a glue layer for the first wiring material and the first dielectric material in a specific embodiment.

As shown in FIG. 7, the method of forming the switching device includes depositing a second adhesion layer 702 overlying the bottom wiring structure material. The second adhesion layer can also be a barrier layer or a blocking layer to prevent chemical reaction of the bottom wiring structure material with, for example, a switching layer material or a contact material subsequently formed. The second adhesion layer can be titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, or others, depending on the embodiment.

Referring to FIG. 8, the method includes forming a contact material 802 overlying the second adhesion layer in a specific embodiment. The contact material can be a doped semiconductor material such as doped polycrystalline silicon, hereafter referred to as polysilicon material in a specific embodiment. The polysilicon material is used as a contact layer between the bottom wiring material and an amorphous silicon switching material in a specific embodiment. In a preferred embodiment, the doped polysilicon material is p+ doped, using impurity such as boron and the likes. In a specific embodiment, the boron has a concentration ranging from about 10E18 to 10E21 cm⁻³. In certain embodiments, the polysilicon material may be further processed to enhance the performance of the switching device. For example, defects or nano metal material may be formed in a surface region of the doped polysilicon material to enhance the performance of the switching device. In a specific embodiment, the polysilicon material allows for controlling and improving switching properties of the amorphous silicon switching material. For other switching materials, such as metal oxide, or others, other contact material may be used, or the contact layer may not be needed. Of course, one skilled in the art would recognize other variations, modifications, and alternatives.

In a specific embodiment, the method forms a switching material 902 overlying the contact material as shown in FIG. 9. The switching material can be an un-doped amorphous silicon material. The un-doped amorphous silicon material can be deposited using a chemical vapor deposition method or a physical vapor deposition method depending on the embodiment. The chemical deposition method can include a chemical vapor deposition process using silane, disilane, a suitable chlorosilane, or a suitable silicon containing gas as a precursor. In a specific embodiment, the un-doped amorphous silicon material may be deposited using a plasma-enhanced chemical vapor deposition (PECVD) process or a low pressure chemical vapor deposition (LPCVD) process. Deposition temperature for the amorphous silicon material can range from about 200 Degree Celsius to about 450 Degree Celsius and preferably at about 350 Degree Celsius to about 400 Degree Celsius. Depending on the embodiment, the amorphous silicon material can be provided at a thickness ranging from about 50 Angstroms to about 1000 Angstroms. In a preferred embodiment, the amorphous silicon material is provided at a thickness ranging from about 100 Angstroms to about 500 Angstroms.

Referring to FIG. 10, the method includes forming a masking layer 1002 overlying the switching material. The masking layer can be a suitable organic photoresist material, or an inorganic hard mask, or a combination of the two, depending on the embodiment. The hard mask can be formed from a dielectric material such as silicon oxide or silicon nitride, or others depending on the application. The hard mask may also be a metal hard mask depending on the embodiment.

In a specific embodiment, the method subjects the switching material, the contact material, and the bottom wiring structure material to a first etching process using the masking layer as a mask to form a first structure 1102 as shown in FIG. 11. The first etching process selectively removes a potion of the first dielectric material exposing a top surface region 1108 of the first dielectric material. The first structure includes at least a bottom wiring structure 1104, and a switching element 1106 in a specific embodiment. The switching element includes at least a first side region 1110. Depending on the hard mask used, remaining portion of the hard mask after etching may be removed. Alternatively, for a hard mask using silicon oxide and a second dielectric layer using a silicon oxide material, the hard mask may be left intact after etch in a specific embodiment.

Referring to FIG. 12, the method includes depositing a second dielectric layer overlying the first structure and exposed portion of the first dielectric layer. The second dielectric layer can include a silicon oxide material or silicon nitride material or a combination depending on the embodiment. In a specific embodiment, the second dielectric layer can be silicon oxide deposited using a plasma enhanced chemical vapor deposition process using TEOS (tetraethyloxysilicate) as a precursor. The silicon oxide material may also be formed using a spin on glass (SOG) technique followed by a suitable curing process. Or a combination of spin on glass and chemical vapor deposition may also be used depending on the application.

In a specific embodiment, the method employs a planarizing process to form a planarized dielectric surface 1302 as illustrated in FIG. 13. This may be accomplished by chemical mechanical polishing, or a non isotropic chemically etch or blanket etch of the second dielectric material in a specific embodiment. As shown, a portion 1304 of the second dielectric material is maintained overlying a top region of the switching element in a specific embodiment. In a specific embodiment, the method includes forming an opening region 1402 in a portion of the second dielectric material to expose a portion of the top region of the switching element as shown in FIG. 14. The opening region is formed by using a second patterning and etching process in a specific embodiment. For example for silicon dioxide as the dielectric material, the etching process may be a dry etch, such as a fluorine-based etching using CF₄, SF₆, or NF₃, as the etching gas. A suitable wet etching technique, such as a HF-based etching may also be used depending on the embodiment.

In a specific embodiment, the method deposits a conductive material 1502 overlying the opening region including the exposed top region of the switching element. As shown, the conductive material forms substantially conformal to the opening region and in contact with the switching element in a specific embodiment. In a specific embodiment, for an amorphous silicon switching material, the conductive material can comprise a silver material. The silver material can be deposited using a physical vapor deposition process such as sputtering or evaporation. The silver material may also be formed using a chemical deposition process such as chemical vapor deposition, electrochemical method such as electroplating, or electrodeless deposition or a combination depending on the application. The method deposits a third adhesion layer 1504 overlying the conductive material as shown in FIG. 15. The third adhesion layer can function as a barrier layer to protect the conductive material, for example, the silver material, from oxidation in a specific embodiment. Third adhesion layer 1504 can serve as a diffusion barrier between conductive material 1502 and subsequent layers, and forms an electrical contact between conductive material and subsequent layers. Third adhesion layer 1504 can be titanium, titanium nitride, tantalum or tantalum nitride, tungsten, or tungsten nitride, depending on the embodiment. Depending on the application, third adhesion layer 1504 can be formed using a chemical deposition such as atomic layer deposition, chemical vapor deposition, and others, or a physical deposition such as sputtering, depending on the application.

Referring to FIG. 16, the method forms a top wiring material 1602 overlying the barrier layer. The top wiring material can be tungsten, aluminum, copper, or others, depending on the embodiment. The top wiring structure material may be deposited using techniques such as physical vapor deposition process such as sputtering, evaporation, and others. The top wiring structure material may also be deposited using chemical deposition such as chemical vapor deposition, electrochemically including electroplating and electroless deposition depending on the embodiment.

In a specific embodiment, the methods includes subjecting the top wiring material together with the barrier layer and the conductive material to a second pattern and etch process to form a top wiring structure for the switching device. In a specific embodiment, the top wiring structure and the bottom wiring structure are spatially arranged in at an angle. In certain embodiment, the first wiring structure and the second wiring structure are spatially arranged in an orthogonal manner. As the first structure including the switching element and the bottom wiring structure is embedded in a dielectric material during etching of the top wiring material, the side region of the first structure is protected from deposited material such as a contaminant conductive material resulting from etching of at least the top wiring material and the conductive material in a specific embodiment. Shorting between the top wiring structure and the bottom wiring structure is thus avoided.

Repeatable resistive switching can be provided by formation or deformation of the filament structure within the switching material. For instance, the repeatable resistive switching can be in response to application, and subsequent variation, of a voltage to the two terminal resistive switching device. As one example, the device can be switching from a high resistance state, e.g., off, to a low resistance state, e.g., on, when the voltage is increased beyond a certain threshold voltage (e.g., a filament formation voltage). The device can be switched from the low resistance state to the high resistance state, e.g., off, when the voltage is decreased lower than a second threshold voltage. In some embodiments, a voltage between the certain threshold voltage and the second threshold voltage can cause a current resistance state of the device to remain unchanged (and utilized, e.g., to read the current resistance state of the device).

In one or more disclosed embodiments, a positive voltage applied to the top wiring structure can generate an electric field(s) causing particles of conductive material 1502 to form within switching material 902. The particles of conductive material 1502 can form a structure (e.g., a filament) extending at least in part across switching material 902. Under suitable circumstances (e.g., application of the positive voltage or the electric field(s)), the filament creates an electrical pathway across switching material 902, resulting in the low resistance state mentioned above. In additional embodiments, a suitable negative voltage applied to the top wiring structure can generate a second electric field(s) that at least in part deforms the filament. Deformation of the filament can interrupt the electrical pathway across switching material 902, resulting in the high resistance state.

In a specific embodiment, the conductive material forms a plurality of conductive material particles including a filament structure in the switching material when a suitable voltage is applied to the top wiring structure or the bottom wiring structure to change a resistance characteristic of the switching material in a specific embodiment. Taking silver material as the conductive material and amorphous silicon as the switching material as an example, upon applying a positive voltage to the top wiring structure, a plurality of silver particles are formed in defect regions of the amorphous silicon material. The plurality of silver particles can include a silver filament structure having a length. The length of the silver filament structure is allowed o changed upon applying a suitable voltage thus changing the resistance of the amorphous silicon material enabling resistive switching o the device. Such a device structure is described in U.S. application Ser. No. 11/875,541, filed on Oct. 19, 2007, commonly assigned, and incorporated by reference in its entirety herein.

Depending on the embodiment, there can be other variations as illustrated in FIGS. 17 a, 17 b 18, and 19. For example, after depositing conductive material 1502 and the third adhesion layer 1504 as in FIG. 15, the method can perform a pattern and etch process to remove a first portion of conductive material 1502 and a first portion of third barrier layer 1504 to expose a surface region 1702 of the second dielectric material as shown in FIG. 17 a and FIG. 17 b. As shown, a second portion of the conductive material and a second portion of the third barrier layer are maintained at least in the opening region, as shown in FIG. 17 a and FIG. 17 b. The second portion of the conductive material remains in contact with the switching element. The method then deposits a fourth barrier layer 1802 overlying the exposed surface region of the second dielectric material and the third adhesion layer in the opening region as shown in FIG. 18.

Referring to FIG. 19. The alternative method deposits a top wiring material 1902 overlying the fourth adhesion layer and performs a pattern and etch process to form a top wiring structure. In a specific embodiment, the top wiring structure and the bottom wiring structure are spatially arranged in an angle and form a crossbar configuration in a specific embodiment.

Depending on the embodiment, there can be yet other variations as illustrated in FIGS. 20-21. For example, taking the intermediately formed structure in FIG. 12, second dielectric layer 1202 is planarized to expose a surface region 2004 of the switching element and to form a substantially planarized second dielectric surface 2002 as illustrated in FIG. 20. A conductive material 2102 is deposited overlying the switching element and the planarized second dielectric surface as shown in FIG. 21. As shown, the conductive material is in contact with the switching element. A third adhesion layer 2104 is formed overlying the conductive material and a top wiring material 2106 is deposited overlying adhesion layer 2104. The method subjects the conductive material, the third adhesion layer, and the top wiring material to a pattern and etch process to form the top wiring structure. In a specific embodiment, the top wiring structure is spatially arranged at an angle to the bottom wiring structure. In a specific embodiment, for the switching element using an amorphous silicon material, a silver material can be used as the conductive material. The third adhesion layer can be titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride and the likes.

Again, depending on the application, there can be other variation as shown in FIGS. 22 and 23. For example, opening region 1402 in FIG. 14 can be filled with conductive material 2202 to form a plug-like structure as shown in FIG. 22. As shown, conductive material 2202 is in contact with the switching element. An adhesive layer 2302 is formed overlying the conductive material and a top wiring material 2304 is formed overlying the adhesive layer as shown in FIG. 23. The method then performs a pattern and etch process to form a top wiring structure at an angle to the bottom wiring structure in a specific embodiment. In a specific embodiment, the top wiring structure is spatially arranged orthogonal to the bottom wiring structure.

Accordingly, embodiments according to the present invention provide a method to form a switching device free of shorts between the top wiring structure and the bottom wiring structure. The present method has been applied to a device structure having an Ag/amorphous silicon/p+ polysilicon configuration and tungsten material as the top wiring material and the bottom wiring material. It should be recognized the present method can be applied in fabrication of a device that uses an inert metal or a noble metal. Example of such devices can include, a switching device using metal oxide as the switching material, at least one of the top wiring material or the bottom wiring material is inert so as not to chemically react with the metal oxide switching material. Etching of the top inert wiring material is feasible using a physical etch. Redeposition of etched conductor materials from the top wiring materials or the bottom wiring materials, or others, on a side region of the switching element can form shorts between the top electrode and the bottom electrode, affecting device performance and yield.

It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. 

What is claimed is:
 1. A semiconductor device including a memory device comprising: a semiconductor substrate; a first dielectric layer disposed above the semiconductor substrate; a first adhesion layer disposed upon the first dielectric layer; a bottom wiring metal disposed upon the first adhesion layer; a first barrier layer disposed upon the bottom wiring metal; a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions; a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles; a second barrier layer disposed upon the conductive metal material; a top wiring metal disposed upon the second barrier layer; and wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material.
 2. The semiconductor device of claim 1 wherein the first barrier layer is selected from a group consisting of: titanium, titanium nitride, tantalum, tantalum nitride, tungsten and tungsten nitride.
 3. The semiconductor device of claim 1 wherein the bottom wiring metal comprises copper.
 4. The semiconductor device of claim 1 wherein the resistive switching material comprises un-doped amorphous silicon.
 5. The semiconductor device of claim 1 wherein the conductive metal material is CMOS fabrication compatible.
 6. The semiconductor device of claim 1 wherein the conductive metal material comprises aluminum; and wherein a plurality of aluminum particles are disposed within defect regions of the resistive switching material and form a filament structure.
 7. The semiconductor device of claim 6 wherein a resistance of the resistive switching material is associated with a filament length of the filament structure.
 8. The semiconductor device of claim 1 further comprising a contact material layer disposed between and in contact with the first barrier layer and with the resistive switching material.
 9. The semiconductor device of claim 8 wherein the contact material is selected from a group consisting of: a doped polysilicon and a doped semiconductor material.
 10. The semiconductor device of claim 1 wherein the semiconductor substrate comprises a plurality of CMOS devices formed therein; wherein the memory device comprises the resistive switching material and the conductive metal material; and wherein the memory device is coupled to at least a CMOS device from the plurality of CMOS devices.
 11. A semiconductor device including a memory device comprising: a semiconductor substrate comprising a plurality of CMOS devices formed therein; a first dielectric layer disposed above the semiconductor substrate; a bottom wiring structure formed upon the first dielectric layer, comprising: a first adhesion layer disposed upon the first dielectric layer; a bottom wiring metal disposed upon the first adhesion layer; and a second adhesion layer disposed upon the bottom wiring metal; the memory device disposed upon the bottom wiring structure, comprising: a resistive switching material disposed in electrical contact with the bottom wiring structure, wherein the resistive switching material comprises a silicon material having a plurality of defect regions; a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles; and wherein at least a group of conductive metal particles from the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material, wherein the group of conductive metal particles comprises a filament structure; and a top wiring structure formed upon the memory device, comprising: a third adhesion layer disposed upon the memory device; and a top wiring metal disposed upon the second barrier layer; wherein the memory device is coupled to at least a CMOS device from the plurality of CMOS devices.
 12. The semiconductor device of claim 11 wherein the first barrier layer is selected from a group consisting of: titanium, titanium nitride, tantalum, tantalum nitride, tungsten and tungsten nitride.
 13. The semiconductor device of claim 12 wherein the bottom wiring metal comprises copper.
 14. The semiconductor device of claim 11 wherein the resistive switching material comprises un-doped amorphous silicon.
 15. The semiconductor device of claim 11 wherein the conductive metal material is CMOS fabrication compatible.
 16. The semiconductor device of claim 15 wherein the conductive metal material comprises aluminum.
 17. The semiconductor device of claim 11 wherein a resistance of the memory device is associated with a filament length of the filament structure.
 18. The semiconductor device of claim 11 wherein the memory device further comprises a contact material layer disposed between and in contact with the bottom wiring structure and with the resistive switching material.
 19. The semiconductor device of claim 18 wherein the contact material is selected from a group consisting of: a doped polysilicon and a doped semiconductor material.
 20. The semiconductor device of claim 11 wherein the bottom wiring metal and the top wiring metal each comprise copper; wherein the first adhesion layer and the second adhesion layer are each selected from a group consisting of: tungsten nitride, titanium, titanium nitride, tantalum and tantalum nitride; and wherein the conductive metal material comprises aluminum. 